The computer industry, with the advances of silicon technology, is constantly faced with the complexities of high speed data busses. The high speed of microprocessor CPUs requires a high speed data bus between the memory subsystem and the front end CPU data bus. However, speed without density of memory is an unbalanced combination. Modern computer systems require increasingly large RAM arrays, and these arrays are packaged in modules of approximately the same size as used in previous, lower capacity memories. Thus, the density of the memory modules, in bits or bytes per square inch of circuit board, is constantly increasing.
The CPU by itself cannot increase computer performance without a high speed memory sub-system and without such a high speed memory the CPU does not perform at the speed it was designed for. When memory access is substantially slower than CPU speed a bottleneck is created between memory and CPU Front End bus. With advances of the Internet, complex application programs and operating systems, memory sub-systems with high-density memory modules have become a necessity.
However, as the density of memory goes up, the capacitive loading of each data bit of the data bus increases. With the increase of the capacitive loading on the data bus, the driver of the data bit line is taxed for higher driving capability. As is well known, when the capacitive loading on a data line increases, the speed at which the corresponding driver circuit can change state on the data line decreases. Thus, on a given data line, the capacitive loading and the speed of data transfer are inversely proportional.
Many bus schemes have been designed to maximize speed in memory modules having increasing memory density. For that purpose, circuits utilizing pass gate switches have been designed into the data path to isolate and reduce the capacitive loading. Patents granted to the present inventor, Chris Karabatsos, include U.S. Pat. Nos. 6,446,158, 6,737,691, and 6,854,042, all intended to remedy this problem.
There are several factors to be considered in the design of such bus circuits transmitting pulse widths in the nanosecond and sub nanosecond range. Solutions include the following:
(a) Data bus widths must be broad enough to satisfy wide data bus requirements of the modern CPU.
(b) High Memory density must be maintained on the same data bus. That is, more Memory Modules are attached to the same data bus, and more connectors appear on the motherboard attached to the bus.
(c) The presence of parasitic resistors, inductors and capacitors (RLC) in the structure of the data bus and on the devices, including connectors, memory modules, printed circuit boards, memory chips and logic chips connected to the bus must be overcome.
(d) Effects of the physical RLC quantities affecting the overall speed by which data can be transported on the bus and thus affecting the overall performance and bandwidth of such bus.
(e) Synchronization of the Data signals and Strobe signals required to latch the data at the destination receiver.
Solutions to these problems in the prior art disclosed systems having dual data banks in which the data rate at each data bank is one-half the data rate at the memory subsystem bus have been described in inventions referenced above. However, further increases in computer speed have created synchronization and data capturing problems in the reading and writing of data between the system bus and the memory banks either directly or indirectly, as described in said prior art.
The present invention provides a significant improvement in memory data rate speed and accuracy with substantial improvement in synchronization between the strobes and data in either direction of transmission and reception and better quality of signal over the prior art. This is accomplished by generating strobe signals and data signals which are synchronized with each other at both ends of the computer DATA BUS memory subsystem.
There are three elements described herein that will allow the high speed reception and transmission of data bits and a termination scheme to reduce reflections and allow multi-drop memory data bit connections in the memory high speed subsystem.
The three elements are:
(a) A high speed data bit latch circuit
(b) A high speed data bit driver circuit
(c) A termination arrangement for high speed data rate multi-drop data bit connections.
The first of these elements is described in the following description of the preferred embodiments of this invention.